I noticed SR latch block needs exactly 5Vdc to trigger. In the first case, there is some filtering which reduces voltage to approx. 4.9V and SR block does not latch.
In the datasheets, there is Minimum HIGH/LOW Level Input Voltage for SR block. Can the library block somehow be modified? Where is 5V limit set? Otherwise, I have to change from low pass to active low pass to get the model working, but this does not reflect the current state of the design.
August 21, 2020
I found that I could get different "SET" behaviour for the two latches, depending on whether the Time-Domain Simulation's Skip Initial was Yes vs No.
So I left Skip Initial at No and put in an explicit Reset at the beginning of the simulation. See V36, NOT8 and red wires.
The two latches now seem to have the same behaviour.
Hope this is of use.
August 22, 2020
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