More inputs on NAND gate

 Gives the right logic results, for sure, but not the right timing results - this solution has 3 delays, instead of the actual 1 of a true 8-input gate. +1 vote by luntb August 21, 2020 You can edit the propagation delay T_PD of each gate to reduce it if you'd like. If you start with @vanderghast's two-layer solution, just cut the T_PD of each gate in half. by mrobbins August 21, 2020 You can also try to use a nand gate made with resistor-transistor logic. It is quite easy to expend it to 8 inputs and has the delay of a single NPN BJT (between each of the 8 inputs and the output). But being made of individual components, it is probably slower than 3 transition times of an IC. Basically, it is made of 8 NPN in series and when all 8 are "ON", they open the path to ground and so, the output (taken after the resistor and before the first NPN, drops to 0 in this case. Not quite economical, energetically, though. by vanderghast August 21, 2020 Correction/ WARNING: the NPN have to be quite performing. At best, they drop 0.2 volt when fully saturated, which implies that the voltage of the output, for 8 of them in series, won't be 0 but 8 times 0.2 = 1.6 volt. Far from being "LOW" , for some logic families. by vanderghast August 21, 2020 Add comment... Please sign in or create an account to comment.

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