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Hi CircuitLab,

I made two versions of a clock devider, one using the data flipflop the other using the toggle flipflop. the one with the D-flipflop works as expected but the T-flipflop fails to toggle the output after the first level shift. Am I forgetting something here or is there some bug in the T-flipflop ?

Br, Martin

Time Simulation plot can be wieved inside the project. It should be public and shared

Hi @MartinLab,

In your circuit, with feedback from ~Q back to T, the circuit will "get stuck" as soon as T goes low, because the flip-flop is being told not to toggle on the next rising CLK edge.

Take a look at this T Flip-Flop demo circuit:

Run the simulation and you'll see how the T input controls whether or not the flip-flop toggles state. Hope that helps.

Hi @mrobbins,

Seems that I misunderstood or mixed-up the behaviour of the T-flipflop. Thanks for the explanation ;-)

Br, Martin