## Double Capacitor w Relay

 I'm building a circuit in which a power source charges a capacitor (C1), which, once fully charged, is supposed to trigger the relay to close. This separates the power source, and enables the second capacitor (C2) to be charged by C1. C1 works well according to the time-domain graph, but there's an issue when it comes to the relay and closing the second part of the circuit. Trying to isolate the issue, I added the "coil" tag, and apparently, the coil is triggered at t = 0, instead of when C1 is fully charged. I'm guessing there's an issue with either the relay or the voltage-controlled switch, but any insight would be appreciated. by icass22 October 28, 2020

 I don't know exactly for what the relay and the switch are intended for, but using a PMOS (MOSFET channel type P) and a NMOS ( MOSFET channel type N), as shown, "could" cover the required functionality, in part. The PMOS will open the circuit as soon as the voltage at its gate reaches VGS(TH) or more. The NMOS will starts to conduct when the voltage at its gates reaches it own VGS(TH). Well, when I say "conduct", that means that a current can flow between the D (drain) terminal and the S (source) terminal of the MOSFET. Here, the Drain of the NMOS is hanging to nothing, so no current would flow. Note the the Source terminals are connected to the voltage-source, the N egative side of the voltage source for the N MOS and the P ositive side of the voltage source for the P MOS. Note that to restart the circuit, you may want to add a switch between the gate terminal of M1, the PMOS, and the ground. As example, if VGS(TH) of M! is 4 volts (generally, but not always, given as -4.0 v, that is, with a negative sign, on datasheet for a PMOS), the circuit will have a close loop through M1, but that loop will get broken when the voltage at Node1 will reach that 4 volt with that condition (within the tolerance given in the datasheet, for that parameter). You won't get more than 4 volt at Node1. Sure, the gate of M1 has some leak, so its voltage could drop, which close the loop previously broken, but that would involve a counter reaction that should recharge the gate within, hopefully, a few femto-second and should not interfere with the conception. +2 votes by vanderghast October 29, 2020 An error in my numerical example: the loop through M1 would open at VS + VGS(TH) = VG, when the numerical value for VGS(TH) is negative. So, for a source at 5 volt, and for VGS(TH) = -4 volt, M1 would break the loop when the voltage at its gate reaches 5 - 4 = 1 volt.(And not 4 volt, as previously mentioned). That would not be enough to "close" any loop through M2 (since the VGS(TH) minimum are around 3 volt). by vanderghast October 29, 2020 Thanks! I hadn't thought about MOSFETs before for such an application, but I'll try them out later today. by icass22 October 29, 2020

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