Unexplained Circuit Change

Hello,

Why would someone change, and/or, what would be the effect of changing, the circuit on the left to the circuit on the right?

Thanks,

James

by Scoidy
November 06, 2020

I'm not as interested in the change of the R4 value and the JFET (unless it's germane) as I am in the function and purpose of the added resistor network from the input and output to ground.

by Scoidy
November 06, 2020

First off, the two JFETs (missing part numbers) are both type J310, as simulated by CL. This is good as it eliminates one potential source of difference.

In the LH cct, J201's gate is floating and the effective bias (wrt source) is 0V. This saturates the FET and the stage is no use as an amplifier!

In the RH cct, R24 provides negative gate bias in conjunction with R19 source resistor. J230 is not saturated and gives a gain of about 2, for small signals.

R25 (if used) would lower the RH stage's output impedance, and thus lower the gain.

I have set the two ccts working in the simulation below, "JFET biassing". I've had to tweak the details a little to make it simulate, and have added a 10mV 1KHz signal for the inputs.

Run "DC Solve" to see biassing levels; run "Time Domain" simulator to see AC amplification (or not, on Output1).

https://www.circuitlab.com/circuit/j3qtyu9w579k/jfet-biassing/

by EF82
November 07, 2020

Thanks EF82. The LH cct is an Alembic Stratoblaster from the early 70s. It produces about 14dB of gain, according to Alembic's literature. Perhaps the resistance of a guitar circuit is used to bias the amp? I have no idea but I do have one and it does amplify. I'll paste a link to a schematic online below.

The RH cct is Alembic's current issue, now called the Blaster. R25 is used.

As you can probably tell, my electronics knowledge is limited. what I'm understanding is that the addition of R24 was to set the bias, although 2 would be pretty weak. And that R25 would set the output impedance in parallel with R22. Is that about right? What I'm trying to understand is why Alembic would make this change.

Thanks again, Scoid

by Scoidy
November 08, 2020

https://www.bing.com/images/search?view=detailV2&ccid=UjRiPOdz&id=8FC4CF2B5032AB6AC7B5A2EC25E516DF0E42039E&thid=OIP.UjRiPOdzbHrPWxAl0H82ugAAAA&mediaurl=http%3a%2f%2fwww.tdpri.com%2fdata%2fattachments%2f168%2f168587-e88806f25c082867460f5fa47de8b81f.jpg&exph=296&expw=400&q=alembic+stratoblaster+schematic&simid=608032258411398956&ck=E7A1EEEDB7EA153E9DC22B5B55A04F1C&selectedIndex=17&FORM=IRPRST&ajaxhist=0

by Scoidy
November 08, 2020

In looking at it again, wouldn't R1 set the bias by making the Source more positive than the Gate? (Similar to a cathode biased tube?)

by Scoidy
November 08, 2020

Hello Scoidy,

Thanks for the info about the circuit. I now know much more about the electronics context (devices connected at input and output) and manufacturing implications.

There will be a short delay before I can post about "why the change" while I finish some investigations into the history and characteristics of the J201 and J230.

In the meantime, more on the "effects" of the change, impacts on bias and gain.

Biassing, R1 and R24

You are correct to say that R1 is positive at its junction with the FET's Source. However, the important voltage is Gate with respect to Source. Tiny and unpredictable leakage currents, both inside the FET's plastic package and in the air, allow the Gate voltage to drift to the same voltage as the rest of the FET electrics in the absence of anything connected to the "floating" input terminal . So, in this case, Vgs is 0V. For most n-channel JFETs, 0Vgs will switch it on fully, causing DC saturation with the given values of R1 and R2.

For normal operation, the LH cct relies on there being a resistive path (even up to several megohms) through the externally connected input device. The RH cct has R24 to maintain Gate bias, even when the input device is disconnected. Additionally, R24 will protect against electrostatic discharge ESD on the Gate.

The analogy with electron tubes is good: both FETs and tubes need a grounding resistance (gate/grid) in order to work predictably with controlled DC bias point; neither will work properly if the gate/grid is open circuit (floating), that is, wrong DC bias point.

Gain

I apologise for not explaining more about gain in my first post: I used the characteristic solely as a go/no-go indicator without being explicit about the details.

The rather unexciting AC voltage gain of 2 (or 3dB) occurs - in the working RH cct - when pot R21 is set at its maximum ohms, 50k. Very roughly, 'low' gain = R20/(R19||50k). C8 has a low enough impedance above about 50Hz that it can be ignored.

The 'high' level of voltage gain occurs when the pot is at 0, in the region of 22 (about 14dB). Roughly: FET transconductance x R20, typically 1 milliMho x 22k Ohms = 22. The exact level at "high" can go up or down as follows:

  • up, when the FET is "hotter" in audio parlance (more technically, with a higher transconductance parameter);

  • down, when there is more output loading - the parallel combination of R22, R25 and the input impedance of the following (pre-) amp stage. I'm sure that the presence of R25 is to trim the gain to an upper limit, so as not to cause overload in subsequent stages. Gain trimming could also be done by reducing R20, but that would have the adverse effect of also reducing the 'low' gain level.

Lots of technical detail here is inevitable: analogue cct design is all about multiple balancing acts between mutually interactive components!

by EF82
November 09, 2020

Hello again!

Why would a manufacturer make a change to a well known product? Manufacturing processes have to keep close control of costs, timescales and performance/quality; any change always has a negative impact on the first two at least, so the reason for a change has to be compelling.

I think the most likely explanation has to do with the original JFET J201. This is an old design and has been overtaken by technology improvements over the years. Most likely the supply chain became too risky. By "supply chain" I mean a dwindling number of silicon foundries making the device in the required format: through-hole (TO-92) vs SMD (SOT-23).

Once a decision was made to drop the origial FET, some cct adjustments were necessary to maintain the expected performance. The J230 has higher gain, hence R25 (see my previous post - Gain). R24 might be to maintain or improve compatibility with piezo pickups which do not have an intrinsic resistive path (previous post - Biassing).

In summary, my suggestion is that both R24 and R25 flowed from an enforced change of FET.

by EF82
November 09, 2020

Thank you very much!

by Scoidy
November 09, 2020
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