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In an attempt to overcome the nReset bug I thought to switch off both, the nReset and the Vcc, this should stop the pulse train to the “customer is waiting” LED.

But look what happens, the “Discharge” switch (pin 7) remains ON, even without power !

What seems to be a miracle is simply another bug of the 555 timer model:

• It’s time to trash it.

BTW @signality ’s “improved 555 timer model” does exactly the same because of the “Latch” element with it’s internal 5V supply … strange … hmmmm … cough ...

Sire, did you genius_ly re-invent CL’s timer model? Or did you know about?

:)

Regards, Sancho

Whilst I agree that this is nonsensical behaviour for the CL - and my - model, I don't think the original 555 timer was designed so that the discharge pin could be taken above the VCC pin. It is therefore likely that there will be a parasitic diode from the discharge pin to the VCC rail.

(In fact there are probably such normally reverse biased diodes from every pin to VCC and from the pins to ground. They are part of most simple IC process's that has to be lived with.)

Hence if VCC is removed as in your example by shorting the VCC pin to ground (V1 at 0V is simply a short circuit) then you might expect the discharge pin in a real device to sit at around 1 diode drop above ground if you source current into it from a higher +ve voltage (your Vcc rail).

So, by accident, in this case, the CL model probably does do what a real device would do.

In my model I did not consider any of the many possible abnormal usage cases of which your circuit is one example. To be honest I was lazy using CL components to build it and I haven't tested it rigorously so there may be other things it doesn't do the way a real 555 would. I did try to build it so that less experienced users could clearly see how it worked compared to a real 555 device datasheet.

:)

This brings us on to the wider point that beyond the basic discrete components resistors, diodes, bipolar, jfet and MOSFET transistors, device models do not normally even attempt to accurately model device behaviour in out-of-spec conditions.

By out-of-spec, I mean outside what the datasheet says about min and max, not beyond the ABSmax ratings.

Even the basic capacitors do not model things like capacitance vs. applied voltage effects, inductors do not normally model saturation and hysteresis effects, bjts do not model reverse Vbe breakdown.

More complex passive devices need more exotic models; flux based inductors and charge based capacitor models (look at some of my attempts to model C vs. V behaviour in a capacitor here in CL before CL introduced the flux based C device). Active discrete devices such as thyristors and triacs and quite a lot of MOSFETs soon explode into huge subcircuits (have a look at the spice model for any MOSFET based on a subcircuit, get a larger monitor to read the subcircuit for an IGBT ... if you can find one that has a model).

Even the simpler multi-transistor devices like opamps, 555 timers and beyond then get into truly massive subcircuits.

Transistor level models might just accurately model out-of-spec behaviour is some cases (subject to some of the caveats already mentioned, and bearing in mind that "passives" inside a chip are often quite dynamic).

However, there are two problems with transistor level models.

1) because they have so many devices, they simulate slowly;

2) Manufacturers do not normally give out such detailed models - at least not unless they are encrypted, which then ties them to a limited number of simulation tools - because they basically tell their competitors far too much about how the device is made;

Hence, more complex device models are normally behaviourally modelled (my 555 circuit is maybe one of the most advanced of many examples I've posted in CL). Behavioural modelling is a compromise. If you try to model every last detail of the behaviour of a transistor level design your compact, fast, nicely converging, behavioural model turns into a sprawling mess that can easily end up running slower and with more convergence problems than the original transistor level model.

Admittedly this is not helped by the fact that many manufacturers give out models that have all sorts of silly errors that render some of them less than useful. I've seen devices that draw currents with no supply connected, models that will only converge when run on a specific simulator, devices that just don't work or they miss out certain critical aspects of the real device behaviour.

The basic rule of simulating any circuit using devices beyond the basic R, L, C, D, Q, M models is that they are only valid for supply voltages within the normal operating range.

If you want to ramp up the supplies from zero for example, you are on your own from zero up to VCCmin!

Again, much of the potential for confusion would be reduced if the behaviour of devices in CL were more clearly documented ...

BTW, at least I can edit my 555 model. Maybe I'll post a more advanced one. Maybe I should start charging for them ...

:-?

@Signality wrote: “I don't think the original 555 timer was designed so that the discharge pin could be taken above the VCC pin. It is therefore likely that there will be a parasitic diode from the discharge pin to the VCC rail.”

Now it comes to the point that we don’t know what CL’s model really wants to represent.

However, the bipolar NE555 / 556 does not have any such diodes to Vcc and the discharge is defined as “open collector”, which clearly suggests to use it with different sources than Vcc.

In fact, up to 15V the current into pin 7 is (far) below 1uA, regardless of the the voltage of Vcc, from GND to 15V or Vcc even disconnected. Thus you can easily switch a relay from the unregulated power supply.

See also: [code] http://en.wikipedia.org/wiki/555_timer_IC [/code] and e.g.[code] http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/DATASHEET/CD00000479.pdf [/code]

But:

• Regarding the CMOS - type I fully understand your concern. There is also a warning in the data sheets:

“Due to the SCR structure inherent in the CMOS process used to fabricate these devices, connecting any terminal to a voltage greater than V+ +0.3V or less than V- -0.3V may cause destructive latchup. For this reason it is recommended that no inputs from external sources not operating from the same power supply be applied to the device before its power supply is established. In multiple supply systems, the supply of the ICM7555 and ICM7556 must be turned on first.”

One would destroy the chip when applying voltage to pin 7 without powering the circuit (and also when switching external voltages above Vcc). That’s one of the reasons why you can’t always substitute the oldies by the modern types (powering up the whole circuit is very critical because of the blocking caps used in circuits with the bipolar type).

Yep, basically simulation can not represent the reality in all the details (I did not know that some commercial models are as bad as you wrote), but one should know the domain and the limits of the model, e.g. by reading some documentation.

I do not expect CL to “damage” such a CMOS device (you know what I mean ...) because of unclear supply conditions.

CL is for the beginners. Few documentation (an advantage).

;-)

This doesn’t mean that the provided elements should not behave like real parts in respect to functionality.

:-((

BTW, I’d hope that CL’s models are optimized and precompiled for the Solver, thus running much faster than kinda “sub-circuit” - ???

Regards, Sancho

Hmmm, careful.

For the ST part you reference,the datasheet implies that the discharge pin can be taken above Vcc.

The Idis(off) parameter in Table 3 on page 5/20 of:

http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/DATASHEET/CD00000479.pdf

quotes:

Discharge pin leakage current (output high) Vdis = 10 V

For 5V < Vcc < 15V

So, this implies that the voltage on the discharge pin can be at 10V with a VCC of 5V.

However this is only implied.

This parameter is not described the same way in other datasheets.

I have not seen it as a definite specified performance parameter and have not seen any manufacturers application notes that show this pin being used that way.

The internal circuit diagram of any device should not be relied upon to support undocumented applications simply because such diagrams are often simplified and do not show the parasitic elements that are inherent to any particular fabrication process. Nor do they always show the detail of any anti-static and overvoltage protection circuitry which may also cause pins to be clamped to supplies and/or ground for voltages above VCC and below ground respectively.

More generally, you have raised an important point about the interchangeability of devices both between different manufacturers and between different technologies.

Always read the datasheet carefully. Do not make assumptions.

This also highlights some of your earlier comments about the modern tendency not to read documentation but to just do it.

Hospitals are full of people who did not read the instructions written on the packaging for their fireworks.

Nuff said?

:)

@Signality: You are aware that I’m are talking about “555 timer” but two different chip generations?

With the CMOS chips: I do not know for “Vcc already established between 5V and 15V” when raising the discharge pin above Vcc.

But I can report that you will damage the 7555 CMOS chip if you first (in usec ! ) power up the chip (+ the surrounding electronics …) by applying power to any pin before the Vcc pin, e.g. by holding it down by a big cap directly at Vcc (pin 8). Maybe not the first time, but try it ten times. I know that from a painful experience when our developers decided to “recycle” a good old schematic but to use the “better and cheaper” CMOS chips instead.

While it is nearly impossible to damage the “old” bipolar 555, the CMOS is very vulnerable. The kind of damage is completely unpredictable, I have seen quite functional chips where the output (pin 3) was working reversed (high instead of low and vice versa), resulting in wheel barrow loads full of fuses and thyristors!

Nope, on the contrary, I do love documentation.

Documentation is good, reading is better, understanding is the best.

The first problem here is that documentation can not explain everything to everybody. Sometimes there may be a reason to hide a little bit, too (you wrote about that).

The second, bigger problem: Joe Average doesn’t like to read documentation. And thus it does not help to print warnings to packings, plastic bags and so on.

Therefor I go for simple products that do not need any documents, but just do what Joe Average expects. As an example, CL’s approach is very close to this paradigm, at least in it’s basics.

Keeping things simple is mandatory for success: You need the masses, not the individualist. (I apologize to all individualists out there!)

Thus I repeat: “It should simply work, no documents, please”.

;-)

Regards, Sancho

@Sancho_P,

Yes, I should have commented about the significant differences between bipolar and CMOS ...

My comment about your earlier comments about people not reading documentation was not referring to you but to comments that you had made in earlier postings about the people you refer to as Joe Public.

(If you can follow that?)

Yes, you can have too much documentation and yes, not giving the whole picture in one go is often necessary to avoid overloading the reader (that is called teaching).

Joe Public may have a right to let off fireworks. However, Joe Public also has a responsibility to read the documentation about them.

It is the hospitals that are full of precisely those Joes who ignore that responsibility.

And far too many of their friends who were all clustered around them at the time trusting that their friend Joe knew what he was doing.

Can't be bothered to read the documentation (CBA) is not an acceptable excuse when there is the potential for harm.

Not everyone using CL is just doing simulations.

Some folk are building and testing real circuits.

They have a right to do so but they also have a responsibility to read the documentation both here in CL and about whatever it is they're trying to do.

They also must also be prepared to recognise and accept that some things are beyond their scope and abilities at a particular point in time and that if they wish to proceed then they must first increase their knowledge and understanding.

If this sounds like an over reaction, just look at some of the projects posted here in CL to see that there are a few that are potentially dangerous with one or two that are potentially lethal.

A couple of examples:

https://www.circuitlab.com/forums/support/topic/hg55u3tb/adding-a-soft-start-to-my-circuit-lm334z-current-regulator/

https://www.circuitlab.com/forums/power-electronics/topic/96fe396y/help-needed-with-shocker-circuit-for-game/

:)

This might go far off topic now, however, it’s our “discussion”, without CL participating :-)

What I wanted to point out is that you can have documents, warnings, license requirements, laws and whatever - most people will just ignore them. Just for coolness, the “kick”. Check with Youtube for bike speeding on public roads, stunts, or check the news for abuse of weapons. We don’t need to look at US movie theaters, just watch neighbors. E.g. one of my neighbors, driving off road while his boys (8 and 10) are standing in the back of his pickup, holding plastic machine guns. What should I do? Sue him? Bad idea, he IS the police here. Shoot him? OK, but how to explain to his wife and kids? And the Judge?

People are dangerous, not only to themselves, the term “responsibility” seems to be outdated in our modern society. There is no role model for them to follow (see politics and lobbyists). “Risk is fun” because young people more likely “feel” than “know” that their future was sold yesterday.

But I’m completely with you with warnings if someone probably doesn’t see the danger, even if it may be useless or may not be understood, because I still believe some people are serious and are worth to be warned of potential harm.

Search for “ophthalmoscope” to find probably such an example (I don’t understand the search results in this case, this is why I ask you to search and didn’t post the link, check the first result).

Regards, Sancho

In fact there is a big problem with the "internal source" in the 555. In the circuit https://www.circuitlab.com/circuit/8ymg74/555-monostable/ I provide a 12 V source and the output only goes to 5V, not close to 12 V as it should according to specs and my experiments with an LM555.

For info:

ST have changed the url for the NE555 timer datasheet:

http://www.st.com/st-web-ui/static/active/en/resource/technical/document/datasheet/CD00000479.pdf

I'm a total newbie to CL and hope to gain more facility. The 'real' chip I'm using is TLC555 (LinCMOS) running from 3 volts. I reckon I'll just have to try things out. ;-)

Great Simulator - thanx to all.

@CVBritton,

Basically, I have built a "better" 555 timer model for CL but you have to understand it's limitations and how to use it.

Having a read through:

https://www.circuitlab.com/forums/support/topic/88ht38p6/bug-report-555-timer-model-nreset/

might help.

Or it might not: depends how strong you can take your coffee ...