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Hello, I am a hobbyist and am having trouble with the digital clock component which I am attempting to use to test a CMOS circuit. I am using Version 43.0.2357.81 m of Google Chrome. The circuit is here: https://www.circuitlab.com/circuit/8cx297/full-adder-cmos-not-working/.

When running the test I found that the voltage node at the output of the clocks and the input of the circuit remained low. I moved the clocks to output to resistors and the clock output remained low. This can be seen when running the time-domain simulation with the currently-configured parameters: 10 s simulation, 0.2 s step (I also ran the simulation with a 0.01 s step and obtained the same results). I have used the same test configuration on similar public circuits and it worked there.

Looks like there's an unreported error in your schematic. If you delete everything except the 3 digital sources and their resistors then the sim runs OK.

It might be partly due to the lower set of 12 MOSFETs not having any supply or ground connections: just connections to the gates.

CL is probably having a hissy fit and has taken its bat home.

If adding the relevant supplies or at least some DC paths to ground via high value resistors, try submitting this as a Bug Report.

You're absolutely right. I had not put in one of the voltage rails.