I just started my computer architecture course at Aarhus University in Denmark. This is a course where we primarily work with the digital logic of circuits, without thinking too much about the analog level (volts, resistances and so on).
I am trying to create a parity bit check circuit here: https://www.circuitlab.com/circuit/5uh3t7/parity-bit-circuit/
But I can't figure out how to simulate it. I already (as you can see) added some 0-bits and some 1-bits as source, but I don't understand how I can read the output bit in order to see if it works.
Can you help me?
November 12, 2013
In your circuit (as posted 13 Nov 2013 0912 GMT),, it has net label errors because you have put spaces in the names.
" I already (as you can see) added some 0-bits and some 1-bits as source, ..."
You also have no digital signal sources.
" ...but I don't understand how I can read the output bit in order to see if it works."
Run this example:
but before your run the time domain simulation, look closely at the Outputs section of the simulation setup panel on the left hand side of the Editor window.
If you click on a wire then the voltage waveform plot for that net will be added to that list.
You can manually enter them using Add Expression. You can also edit the ones already in the list by clicking on the little pencil button next to them.
See this example too:
November 13, 2013
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