Positive-Edge Trigger Monostable PUBLIC

I was looking for a way to transform a clock signal into really short impulse to trigger another device.

Normally we do this by transforming your clock signal into short spikes using a simple differentiator then feed this to a monostable which will generate your final pulse of length T.

All the solution I found was time dependent of my monostable trigger(spike). That means that I wasn't unable to achieve an output pulse of length shorter than my input trigger. Then I make some search and all the solution which were allowing me to achieve this was too complicated for nothing.

I came up with this, it does all that with minimal parts count. Actually its a kind of delay line. The output pulse is determined basically by R1C1, you need to consider the VIH of the NOT input to make the proper timing calculation. If you need a lot of precision you might include in your calculation the max propagation delay of logic parts.

How it works:

When CLK1 is in active state (HIGH): 1. The AND1 output is HI. 2. BUF1 starts to charge C1 through R1. 3. When C1 voltage reaches VIH of NOT1, NOT1 output goes LOW and AND1 output goes LOW.

When CLK1 is in idle state (LOW): 1. AND1 output is LOW 2. BUF1 discharge C1 through R1, 3. When C1 voltage reaches VIL of NOT1, NOT1 output goes HI.

To calculate timing:

t = -log((V - V_c / V )R * C

To calculate voltage at a specific time:

V_c = V - ( V * e ^(-t/(R*C)) )

Where: V = Supply Voltage Vc = Output Voltage to reach (In this case VIH) R = Resistor value C = Capacitor value