how to do a CMOS transistor level implementation
March 26, 2022
A CMOS is a combination of NMOS and PMOS.
If you remember that a NMOS or a PMOS, as a switch, are OFF when Vgs = 0, or when Vg = Vs if you prefer, then a NMOS will be on for Vg > Vs, or when the input is ON, and it would be te reverse for a PMOS.
In short, if the input A (at the gate) is on the NMOS, the output will be A, but for a PMOS, the output will matches NOT A.
Next, if the transistors are in series, that is a AND, while if they are in parallel, that is an OR.
Technical detail, but important, check for possible short-circuit, for when the transistor is ON. If the only resistor in the path from Vcc to ground is Rds(on), you may vaporize your MOSFET.
In this example, the transistor are in series, so it is an AND. It is a PMOS which connects the input A, so the output will imply (NOT A). An NMOS is connected to the input B, so the output will be ( B). The output will thus be ( NOT A ) AND (B).
The pulldown resistors are required to discharge the gates. Without them, the gate is like a capacitor and once charged, will stay charged for "some" time. We cannot use a 0 ohm resistor since then, the gate will always be at ground. On the other hand, the gate will take a time proportional to R * C ( C = capacity of the gate) to turn on or off. So, the pull down resistor should not be too large, otherwise, the logic gate could be slow to react.
Rsafe is required for two reasons.
Without it, that is, at 0 ohm, the output will always be at the voltage of the source, so the output would always be high since no component will be able to drop some voltage between the source and the output node. If one of the resistors is OFF, the current is ZERO, so Rsafe drops 0 volt ( Vrsafe = I x R = 0 x Rsafe = 0 ), The output voltage is thus at 5V, which is what we want in that case.
If both resistors are ON, Rsafe limits the current through the loop. Otherwise, 5 V = 2Rds(on)I will imply a large current I.
But, adversely, Rsafe also limits the current available by the external circuit connected to the "output" node. That is why, in IC, there is an extra stage to compensate for that limitation. So, consider that circuit as a "start" rather than a "nec plus ultra" commercial example.
Not really sure that this answers your question, though. Please, be more precise about what you want to do if it does not.
March 27, 2022
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