How program counters with feature "Read from bus Enable", "Write to bus Enable" and "Count Enable" is designed?

I have been designing program counter that has a features like "Read from bus Enable", "Write to bus Enable" and "Count Enable".

I have already designed binary counter

And Read from bus Enable using almost the same parts.

So I'm having a problem with connecting those two designs. To be more specific: In order to binary counter operate all J and K inputs of JK flip flops should be high (1 or true) and output (Q) of 1st JK flip flop should be connected to the clock of the 2nd JK flip flop.

However, in order to "Read from bus Enable" operate J and K inputs of JK flip flops should be opposite (when J = 1, K = 0 or when J = 0, K = 1) and clock input of JK flip flops should be connected to clock (not to output of previous clock)

These two design seems to me conflicting. So my question is:

  • Is it possible to connect them with my current design? How?
  • How program counters with "Read data from bus" feature are designed?

P.S. I wanted to understand design of Synchronous 4-Bit Binary Counters (link to binary counter) but it was too hard for me. Please try to explain with in a simple way (with images if it is possible). Because I have limited knowledge in electronics and I'm more a visual learner.


by mardon
November 10, 2018

Possibly a quick look at MC4018B might help. This has 'jam' inputs which can act as Read-from-Bus and has a synchronous counter function. Your Write-to-Bus requirement can be met by a tri-state buffer.

Sorry, this uses D-flops in a Johnson ring, rather than your preferred JK-flops but it does show how the requirement can be met.

by mikerogerswsm
November 11, 2018

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