D Flip-Flop with Async Clear PUBLIC

Created by
Created January 10, 2013
Last modified July 12, 2018
Tags digital   flip-flop   ic   user-library  

Summary

Library Component - D Flip-Flop implemented from NAND gates with async Set and Clear inputs. Includes time-domain input test vector.

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Comments

I just started a thread in the feature request forum requesting a component like this in the Digital Primitives library - there are currently no primitives that mix clocked and async operation like this, and I needed one. Hope this helps somebody else.
Avatar for jvmatl
by jvmatl
January 10, 2013

I agree. For those who may want to support here is the link

https://www.circuitlab.com/forums/feature-requests/topic/mf7w6e8b/please-add-an-asynchronous-clear-input-to-the-library-d/
Avatar for avsteele
by avsteele
June 12, 2024

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