|Created||September 30, 2013|
|Last modified||September 30, 2013|
|Tags||power-supply pwm switching|
An edge-defined gate drive signal is produced by a CSV voltage source, and modulated to form a power supply feedback loop.
V1 and its PWL (piecewise linear) defined periodic drivetrain is modulated onto the gate of M1. When the output voltage is sufficiently high, the comparator CMP1 output goes high, and the clocked inhibit digital signal goes through the diode D1 to prevent the gate of p-channel M1 from turning on.
The feedback loop causes the output voltage to stay near the reference voltage of 2.5V, and it will do so for a fairly wide range of reference voltages as well as load currents!
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