|Created||March 07, 2012|
|Last modified||March 18, 2012|
|Tags||mechanical pull-up switching time-constant|
A demonstration of how to debounce a switch with an RC and a comparator.
SW1, SW2 and R1 are copied from my Bouncy Switch schematic. SW2 represents a physical switch, but when closed SW1, a virtual switch representing switch "bounce" etc. can intermittently open the connection. SW_OUT is the noisy output of such a switch.
SW3 and SW4 reproduce this effect, but they drive an RC load. As soon as the switch closes, the node SW_FLTR goes low. But when the switch opens, it takes a while for the node to go high, based on the RC time constant. Values chosen here such that during the glitches controlled by CLK2 and SW4, the SW_FLTR node cannot rise to the 3V comparator threshold during the short glitches.
The comparator plus MOSFET is a simple way of emulating a cheap open-collector/open-drain comparator such as the ubiquitous LM339. Thanks to @mrobbins for suggesting I change the FETs to 2N7000 - much more appropriate than my first choice (which just used the default choice of MOSFET). This reduced a "glitch" at the output due to the parasitic capacitance of the FET.
The first comparator only modifies the response of the switch's turn-off edge. This delays the low-high transition by 1ms, but not the high-low transition. The second comparator is not needed for deglitching (a switch does not have intermittent "shorting" when in the "off" state), but by applying the same time constant to the other edge, we get a debunked output that reflects the accurate timing of the switch closure, but delayed at both edges by 1 ms. (I plan to use this on rotary encoders; in that case I need to look at the relative timing of switch closures; a consistent delay on all edges is a suitable solution that will eliminate potential errors.)
BENCHMARKING: I ran (an earlier version of) this circuit for 20ms with 1us time steps in three browsers under Mac OSX (10.7.3):
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