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Created | May 17, 2012 |

Last modified | January 02, 2013 |

Tags | active-rectifier diode full-wave-rectifier precision-rectifier |

One of many possible precision fullwave rectifiers using opamps.

This one requires a low impedance signal source and a high impedance load to operate correctly.

Here's how the circuit works.

This version of the full wave rectifier the following design rules:

It requires a low impedance signal source and a high impedance load to operate correctly, i.e;

`Rsrc1 << R3`

`Rload1 >> R2`

`R1 = 2*R2`

`R3 = R2`

For +ve half cycles D2 conducts and makes the inv i/p of OA1 sit at 0V. D1 is reverse biased. This makes the load on OA1 o/p look like R1//(R2+R3) (where // = in parallel with).

This simplifies to:

`R1/2`

The output is:

`V(out) = V(in)*R2/(R2+R3)`

which simplifies to:

`V(out) = V(in)/2`

For -ve half cycles, D2 is reverse biased and D1 conducts. The open loop gain of OA1 removes the diode drop by setting the o/p of OA1 such that the inv i/p of OA1 sits at 0V (that's what is meant by a virtual earth input, it sits at a fixed voltage irrespective of other conditions). This means that OA1 operates as an inverting x0.5 gain stage where:

`V(out) = -V(in)*R2/R1`

which simplifies to:

`V(out) = -V(in)/2`

Under these conditions, the load at in is `2*R3*R1/(2*R3+3*R1)`

which simplifies to:

`R1/4`

Note that, due to the non-linearity of the input resistance, it is recommended that this circuit is driven by a direct coupled low impedance source, i.e. some form of opamp buffer or gain stage.

If the circuit is driven by from any form of fixed amplitude AC coupled input and you have satisfied the design rules above but still see some mismatch between the successive rectified peak amplitudes at V(out) then that is because the startup transient due to the input coupling time constant has not yet settled out.

You need to run the sim for several times the time constant set by any input coupling cap and the input resistance to allow that to settle out then look at the last few cycles. If there is more than one AC coupled stage prior to the rectifier input buffer then allowance must be made for the additional time constants.

It is not easy to do that in CL because you have to wait for the whole sim to run then zoom into the last few ms of the whole plot. Unlike in more advanced spice simulators, you cannot run the sim for some time, T, but just plot the traces for T-t where t < T.

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