|Created||April 12, 2012|
|Last modified||May 18, 2012|
|Tags||amplifier bjt convergence feedback initial-conditions jfet level-shift startup|
This is a subset of "Trouble 1". This is the core voltage gain and DC bias feedback which would exhibit convergence difficulty on the old FET model. CircuitLab has fixed the model. This circuit now operates properly.
This is the core amplifier circuit of "Trouble1" which was used to illustrate a convergence problem. CircuitLab has fixed the convergence problem and this circuit now operates properly.
The intent of this circuit was to have its input referenced to ground and be of high impedance. The circuit provides substantial power gain for driving communications cable. This subset of the circuit provides high impedance and voltage gain. It should have an emitter follower stage following it to provide current gain and isolation for driving cable.
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