Forums » CircuitLab Support Forum

I am trying to simulate PC3 of a 4046 PLL, which is basically an SR flip flop with feedback. When I go to simulate it, it gets to about 0.5% and then the estimated time remaining goes up by several minutes for each actual wall-time second that goes by. It never finishes.

I am trying to run a time domain simulation of 0-20 seconds with a step of 0.01 seconds.

Browser: Chrome Version 84.0.4147.125 (Official Build) (64-bit) OS: Ubuntu 20.04

Circuit: https://www.circuitlab.com/circuit/kepg69k6t5nd/pc3-and-filter/

Any help would be greatly appreciated.

Suppose both f1 and f2 are at a high voltage, such that they're both interpreted as digital logic high (1).

In this case the AND1 and AND2 gates are effectively just passing through the other signal (~Q and Q, respectively).

At that point, I think you've just made an oscillator that will keep changing state as fast as the propagation delays allow. The simulator then has to compute and store an enormous amount of data.

My suggestion would be to try changing the propagation delay of LTCH1 to be much longer: for example, double-click LTCH1 and set it's T_PD to be 1e-3 or 1e-4. This limits the internal oscillation frequency so that the simulation can run in a reasonable amount of time.

I tried to simplify the circuit somewhat and ended up with this:

Run the simulation and take a look at the difference for when CLK2 is faster or slower than CLK1. Not perfect but I think we're getting somewhere.