Forums » General Electronics Discussion

Hi, I'm designing part of a circuit to detect dawn/dusk with a built-in ~10 minute delay which will serve as an input to some CMOS logic. It's the first such circuit I've designed and though it seems to behave correctly in CircuitLab I have a couple of questions:

1. Should there be a pull-up resistor after CMP1?
2. Is using an RC circuit for the delay efficient/sensible or should I use a some sort of timer instead?
3. Could the entire thing be done more simply/efficiently?

Thank you!

Tim

1) Depends on the real device you choose. CMP1 and CMP2 in your simulation are modified CL opamps which have rail to rail push-pull outputs rather than dedicated comparator models.

You can choose real comparators that have push-pull or open collector/drain outputs. Push-pull outputs don't need a pullup. Open collector/drain outputs do.

2) 10 minutes is a long time for an RC circuit but is possible. Avoid large R/small C because the circuit will be more susceptible to leakage due to moisture cause by condensation than will small R large C. Timing with an RC may be a bit variable with component tolerances, temperature and ageing.

A digital solution using a higher frequency clock oscillator and a divider chain may give you a more repeatable time but if the oscillator itself is an RC part then most of the same problems can occur.

If you can find a source of them, then the old 4060 14-bit (÷16,384) ripple counter with internal oscillator is a nice solution:

http://uk.farnell.com/jsp/search/browse.jsp;jsessionid=DSHJJ1SRWNDO0CQLCIPZNFQ?N=0&Ntk=gensearch&Ntt=cmos+4060&Ntx=mode+matchallpartial&exposeLevel2Refinement=true&suggestions=false&ref=globalsearch&_requestid=99291

3) If you keep the RC solution, you would be well adivised to add a small amount of hysteresis from CMP1 output to CMP1 non-inverting input. This will stop the output of CMP1 jittering at the threshold.

Note to model an open collector comparator, you can use a voltage controlled switch like this:

If you set the hysteresis to 0 then you can add your own hysteresis by putting a resistor from the out to the + input together with some source resistance at the + input.

To make the hysteresis more predictable, you may want to add some series R between the junction of LDR and R2 and the + input to swamp the variation in Thevenin source resistance due to the variation in the resistance of LDR

Another way to make a behavioural open collector/drain comparator:

Hi, thanks for the replies:

1) I'm planning on using the LM393N, which is a dedicated comparator and is open-collector (I think). So pull-up resistor it is.

2) What counts as big/small? Would changing to 100k Ohms + 3300 uF be more appropriate?

The timing and variance of the delay isn't that important. It's only there to have the output based on a sort-of running average of the last 5-10 minutes to avoid false triggers such as if a cloud passes in front of the moon for a few minutes.

If this was done digitally wouldn't it still require significantly smoothing the input or doing something else to avoid the false triggers, rather than just having a delay?

3) Ok.

I tried modelling the comparators with voltage-controlled switches but I believe + and - are connected and when the current reverses at CMP2 strange things happen - the capacitor doesn't like it. In the LM393N I think they're both connected to ground instead and so this shouldn't be an issue?

Thanks for the help - this is very useful!