|Created||November 13, 2011|
|Last modified||February 08, 2021|
|Tags||dac digital op-amp|
A four-bit digital counter is implemented with discrete digital logic and registers. Those four bits are fed into an op-amp based digital-to-analog converter (DAC).
This example highlights the advanced mixed-mode simulation support included in CircuitLab. If you know of any other software that makes it as easy to simulate mixed-mode (analog and digital at the same time) circuits, let us know!
XOR1 and AND1 form what's called a "half adder" -- adding a 1 to whatever input bit Q0 is. There are a total of four half adders, and four bit registers. On the rising edge of every clock, the next computation is clocked into and stored in the registers.
The XORs compute the column sum of each addition. The ANDs compute the carry bit of each addition.
In this way, this circuit counts 0, 1, 2, 3, ... 15, and then wraps back around to zero. (The output of AND4 is an "overflow" bit representing when the entire counter has wrapped around.)
These bits are then summed using binary-weighted resistor values into the op-amp's virtual ground. The output is proportional to the total current fed there, and that current is dependent on whether each bit is 1 or 0, in combination with the resistor value setting the amount of current for that bit.
Load the simulation by clicking "Open in editor" above, and then click "Simulate" at the bottom. Run a time domain simulation.
Can you extend it to 8 bits?
May 21, 2013
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