Created by
Created November 13, 2011
Last modified May 17, 2012
Tags digital   mosfet   pull-up  

Summary

Two n-channel MOSFETs plus one pull-up resistor form a two-input NAND logic gate.


Description

When both A and B are high, the output voltage is pulled low. Otherwise, the output voltage is high.

A few things to try in CircuitLab

Load the simulation by clicking "Open in editor" above, and then click "Simulate" at the bottom. Run a time domain simulation.

Verify digital operation

Plot A, B, and out versus time. You should verify that the logic performs the correct operation.

Power consumption

How much current is consumed when the output is in the low state?

See also

MOSFET (CMOS) NAND gate:

MOSFET and resistor NOR gate:

MOSFET (CMOS) NOR gate:


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Revision History

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